Static Timing Analysis (STA) is a key step in the design of high speed Very Large Scale Integrated (VLSI) circuits. STA is used to verify that a VLSI circuit-design performs correctly at a required frequency before it is released for chip manufacturing. A circuit-design must be timing closed prior to manufacturing. Timing closure refers to the process of designing and optimizing (or tuning) a circuit such that applied electrical signals can traverse through the circuit within specified timing values. STA guides and validates the completion of timing closure. During STA, a circuit-design is represented as a timing graph; the points in the design where timing information is desired constitute the nodes or timing points of this graph, while electrical or logic connections between these nodes are represented as timing arcs of the graph. STA is performed typically at the logic gate level using lookup-table based gate timing libraries. It may involve some runtime expensive circuit simulation for timing calculation of wires and gates using current source model based timing libraries.
In modern sub 45 nanometers chip manufacturing technology, VLSI designs are increasingly getting larger in terms of size and complexity. Large Application Specific Integrated Circuit (ASIC) designs can include several hundred million logic gates. Performance centric designs like microprocessor designs can include custom circuit designed components that achieve aggressive frequency targets, and can contain upwards of one billion transistors. STA of the aforementioned designs would like to employ circuit simulators to achieve accurate timing calculations. However, the run-time intensive nature of circuit simulation is impractical for large designs, especially where timing runs are made daily during the design cycle of a chip. In essence, static timing analysis of modern large circuits as a single flattened design is run-time prohibitive. This has led to the development of a hierarchical timing flow wherein a circuit design is partitioned into components. A component may be partitioned further into sub-components in a recursive fashion. By way of an example, a typical microprocessor design is partitioned into several components referred as cores, each core is partitioned into components referenced units, wherein each unit is partitioned into components further referred as macros. Illustratively, a core level of hierarchy can contain a set of units connected using wires and additional gates that do not become part of any component. Similarly, a unit level of hierarchy can contain a set of macros connected by way of wires and additional gates that do not form part of any component. For ease of notation, the term “component” will hereinafter imply a sub-component or component (e.g., a macro, unit, or core) without any loss in generality.
Referring to FIG. 1, a unit component containing two components (macros) is illustrated, namely, Macro-1 and Macro-2, and additional gates and wires. In a hierarchical timing flow, STA and timing closure for each component is performed in isolation or “out-of-context” (OOC). At this level, the component is not connected to any other part of the circuit outside its scope, which may be followed by the generation of a simplified timing macro-model for the component. A commonly used timing macro-modeling style involves pruning of certain internal latch-to-latch paths in the component to create a simplified component model. An alternate style of timing macro-model can consist of a single gate timing model of the component with additional information about the boundary wires. The timing macro-model is subsequently used in place of a component at the parent level(s) of hierarchy, wherein the hierarchical timing approach can enable a faster timing analysis and productivity at the parent level since the macro-models have a reduced complexity. For simplicity of notation, the term component can be interchanged hereinafter by its timing macro-model when it is used at the parent level(s) of hierarchy.
Timing optimization or closure (for example: chip area or power optimization while satisfying timing specifications) of a component involves design-updates. Post timing closure, the updated component is intended to be plugged into all instances of the component at the parent level(s) of hierarchy. However, timing closure of the component is dependent on the timing constraints at its boundary (primary input and primary output) pins. For explanatory illustrative purposes, the timing closure for a data path starting from a primary input (PI) of a component leading to either a latch or a primary output (PO) can dependent on when the electrical signal reaches the PI, which in turn is known accurately only at the parent level of hierarchy. Alternatively, at the parent level of hierarchy, the timing information at the component PI depends on electrical characteristics of the wire and the gate within the component that are connected to the PI. Any change to the resistance-capacitance (RC) parasitics of the wire or a change to the gate (which causes a change in the gate input pin capacitance) impacts the timing information at the PI that is subsequently used for the timing constraint computation. This establishes a loop-like situation, wherein timing closure of a component depends on boundary constraints from the parent level, and accurate generated constraints at the parent level require the presence of the optimized component. A way to solve the problem is to use a feedback constraint generation process, wherein multiple iterations of a component's timing closure is performed during the chip design life-cycle. In each iteration of using a component at the parent level of hierarchy, boundary constraints for the component are generated, and subsequently used to perform STA and timing closure of the component “out of context”. Timing closure with new boundary constraints results in an updated version of the component (due to design optimization during timing closure). The updated version of the component is then used for the next iteration of feedback constraint generation in an iterative fashion until there are no further updates.
FIG. 2 illustrates a parent level of hierarchy 200 that contains a sub component with two primary inputs: DATA and CLOCK, and one primary output: OUT. A gate 201 drives the input DATA of the component through a hierarchical wire that consists of two parts: 202 and 203. These parts denote the portion of the wire outside and within the component, respectively. The hierarchical wire finally feeds a gate 204 within the component. It is assumed for illustration that the signal arrives at the input of gate 201 at time 10 units (implies that the arrival time is 10 units) and with a slew of 8 units. The delay through gate 201 and the slew at the output of 201 is a function of the electrical parasitics of 202, 203, and 204's pin capacitance. The slew at the output of 201 is subsequently used to compute the delay across the hierarchical wire. It is assumed that the total delay across 201 and 202 is computed as 5 units, and thus the arrival time (AT) of the primary input DATA is (10+5=) 15 units. It is further assumed that the slew at DATA is computed as 25 units. As part of traditional feedback constraints generation, these values are captured as illustrated in table 205. In the table, for each primary input of the component, an arrival time and slew is captured. Similarly, for each primary output (PO), a required arrival time is captured. Additional information is captured as part of this process, but is not described here for brevity.
FIG. 3 depicts the out-of-context timing and use of feedback constraints for a component 300. It is assumed that the component was used at a parent level of hierarchy 200 as illustrated in FIG. 2 to obtain feedback constraints. From the feedback constraints as illustrated in table 205 of FIG. 2, the arrival time (AT) and slew on the input DATA is set as 15 units and 25 units, respectively. This information represents accurate timing information from the parent level of hierarchy provided the parasitics of the wire 303 and the gate 304 are not altered. Timing closure of the component may, however, update either 303 or 304, or both as illustrated in FIG. 3 by either routing the wire 303 on different metal layers within the VLSI chip or by choosing a different gate-size for 304. Such updates change the electrical parasitics of the wire or the gate input pin capacitance. Traditional or prior art feedback constraints do not react to such design changes and assumes the AT and slew on the input DATA is constant. More particularly, looking at the parent level of hierarchy in FIG. 2 indicates that a change in 203 or 204 (corresponds to 303 and 304 in FIG. 3) may impact the delay through 201 as well as the slew at the output of 201. This in turn may impact the delay across 202, and thus the AT and slew at the input DATA could be impacted. Not accounting for this change to the feedback constraint at any primary input could cause inaccurate out-of-context (OOC) timing for the component, which may require extra design closure iterations, thereby negatively impacting designer productivity. This is indicative of a need for a method of generating and using dynamic load-sensitive feedback constraints that react to the aforementioned design changes and thereby facilitate accurate OOC timing.